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标题: SDRAM仿真文件sdr.v是怎么生成的？ [打印本页]

作者: Alex193 时间: 2021-2-15 20:43
标题: SDRAM仿真文件sdr.v是怎么生成的？
请问这个module sdr (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);仿真模块是怎么生成的？
/**************************************************************************
*
* File Name:  sdr.v
*    Version:  2.2
*       Date:  October 12th, 2010
*       Model:  BUS Functional
* Simulator:  Model Technology
*
* Dependencies:  None
*
*       Email:  modelsupport@micron.com
*    Company:  Micron Technology, Inc.
*
*  Description:  Micron SDRAM Verilog model
*
* Limitation:  - Doesn't check for refresh timing
*
*       Note:  - Set simulator resolution to "ps" accuracy
*             - Set Debug = 0 to disable $display messages
*
* Disclaimer:  THESE DESIGNS ARE PROVIDED "AS IS" WITH NO WARRANTY
*             WHATSOEVER AND MICRON SPECIFICALLY DISCLAIMS ANY
*             IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR
*             A PARTICULAR PURPOSE, OR AGAINST INFRINGEMENT.
*
*             Copyright ?2001 Micron Semiconductor Products, Inc.
*             All rights researved
*
* Rev  Author       Date       Changes
* ---  --------------------------  ---------------------------------------
* 2.3  SH             05/12/2016  - Update tAC, tHZ timing
*    Micron Technology Inc.
*
* 2.2  SH             10/12/2010  - Combine all parts into sdr_parameters.vh
*    Micron Technology Inc.
*
* 2.1  SH             06/06/2002  - Typo in bank multiplex
*    Micron Technology Inc.
*
* 2.0  SH             04/30/2002  - Second release
*    Micron Technology Inc.
*
**************************************************************************/

`timescale 1ns / 1ps

module sdr (Dq, Addr, Ba, Clk, Cke, Cs_n, Ras_n, Cas_n, We_n, Dqm);

`include "sdr_parameters.h"

input                      Clk;
input                      Cke;
input                      Cs_n;
input                      Ras_n;
input                      Cas_n;
input                      We_n;
input    [ADDR_BITS - 1 : 0] Addr;
input    [BA_BITS - 1 : 0] Ba;
inout    [DQ_BITS - 1 : 0] Dq;
input    [DM_BITS - 1 : 0] Dqm;

reg       [DQ_BITS - 1 : 0] Bank0 [0 : mem_sizes];
reg       [DQ_BITS - 1 : 0] Bank1 [0 : mem_sizes];
reg       [DQ_BITS - 1 : 0] Bank2 [0 : mem_sizes];
reg       [DQ_BITS - 1 : 0] Bank3 [0 : mem_sizes];

reg                [1 : 0] Bank_addr [0 : 3];             // Bank Address Pipeline
reg       [COL_BITS - 1 : 0] Col_addr [0 : 3];                // Column Address Pipeline
reg                [3 : 0] Command [0 : 3];                // Command Operation Pipeline
reg                [1 : 0] Dqm_reg0, Dqm_reg1;             // DQM Operation Pipeline
reg    [ADDR_BITS - 1 : 0] B0_row_addr, B1_row_addr, B2_row_addr, B3_row_addr;

reg    [ADDR_BITS - 1 : 0] Mode_reg;
reg       [DQ_BITS - 1 : 0] Dq_reg, Dq_dqm;
reg       [COL_BITS - 1 : 0] Col_temp, Burst_counter;

reg                         Act_b0, Act_b1, Act_b2, Act_b3; // Bank Activate
reg                         Pc_b0, Pc_b1, Pc_b2, Pc_b3;    // Bank Precharge

reg                [1 : 0] Bank_precharge    [0 : 3];    // Precharge Command
reg                         A10_precharge       [0 : 3];    // Addr[10] = 1 (All banks)
reg                         Auto_precharge    [0 : 3];    // RW Auto Precharge (Bank)
reg                         Read_precharge    [0 : 3];    // R  Auto Precharge
reg                         Write_precharge    [0 : 3];    //  W Auto Precharge
reg                         RW_interrupt_read [0 : 3];    // RW Interrupt Read with Auto Precharge
reg                         RW_interrupt_write [0 : 3];    // RW Interrupt Write with Auto Precharge
reg                [1 : 0] RW_interrupt_bank;             // RW Interrupt Bank
integer                      RW_interrupt_counter [0 : 3];    // RW Interrupt Counter
integer                      Count_precharge    [0 : 3];    // RW Auto Precharge Counter

reg                         Data_in_enable;
reg                         Data_out_enable;

reg                [1 : 0] Bank, Prev_bank;
reg    [ADDR_BITS - 1 : 0] Row;
reg       [COL_BITS - 1 : 0] Col, Col_brst;

// Internal system clock
reg                         CkeZ, Sys_clk;

// Commands Decode
wire    Active_enable = ~Cs_n & ~Ras_n &  Cas_n &  We_n;
wire    Aref_enable    = ~Cs_n & ~Ras_n & ~Cas_n &  We_n;
wire    Burst_term    = ~Cs_n &  Ras_n &  Cas_n & ~We_n;
wire    Mode_reg_enable  = ~Cs_n & ~Ras_n & ~Cas_n & ~We_n;
wire    Prech_enable    = ~Cs_n & ~Ras_n &  Cas_n & ~We_n;
wire    Read_enable    = ~Cs_n &  Ras_n & ~Cas_n &  We_n;
wire    Write_enable    = ~Cs_n &  Ras_n & ~Cas_n & ~We_n;

// Burst Length Decode
wire    Burst_length_1 = ~Mode_reg[2] & ~Mode_reg[1] & ~Mode_reg[0];
wire    Burst_length_2 = ~Mode_reg[2] & ~Mode_reg[1] &  Mode_reg[0];
wire    Burst_length_4 = ~Mode_reg[2] &  Mode_reg[1] & ~Mode_reg[0];
wire    Burst_length_8 = ~Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];
wire    Burst_length_f =  Mode_reg[2] &  Mode_reg[1] &  Mode_reg[0];

// CAS Latency Decode
wire [2 : 0] Cas_latency =  {Mode_reg[6],  Mode_reg[5], Mode_reg[4]};

// Write Burst Mode
wire    Write_burst_mode = Mode_reg[9];

wire    Debug          = 1'b1;                         // Debug messages : 1 = On
wire    Dq_chk          = Sys_clk & Data_in_enable;    // Check setup/hold time for DQ

assign Dq             = Dq_reg;                      // DQ buffer

// Commands Operation
`define ACT    0
`define NOP    1
`define READ    2
`define WRITE    3
`define PRECH    4
`define A_REF    5
`define BST    6
`define LMR    7

// These timing dynamically adjust based on CAS Latency
time  tAC, tHZ;

// Timing Check variable
time  MRD_chk;
time  WR_chkm [0 : 3];
time  RFC_chk, RRD_chk;
time  RC_chk0, RC_chk1, RC_chk2, RC_chk3;
time  RAS_chk0, RAS_chk1, RAS_chk2, RAS_chk3;
time  RCD_chk0, RCD_chk1, RCD_chk2, RCD_chk3;
time  RP_chk0, RP_chk1, RP_chk2, RP_chk3;

initial begin
      Dq_reg = {DQ_BITS{1'bz}};
      Data_in_enable = 0; Data_out_enable = 0;
      Act_b0 = 1; Act_b1 = 1; Act_b2 = 1; Act_b3 = 1;
      Pc_b0 = 0; Pc_b1 = 0; Pc_b2 = 0; Pc_b3 = 0;
      WR_chkm[0] = 0; WR_chkm[1] = 0; WR_chkm[2] = 0; WR_chkm[3] = 0;
      RW_interrupt_read[0] = 0; RW_interrupt_read[1] = 0; RW_interrupt_read[2] = 0; RW_interrupt_read[3] = 0;
      RW_interrupt_write[0] = 0; RW_interrupt_write[1] = 0; RW_interrupt_write[2] = 0; RW_interrupt_write[3] = 0;
      MRD_chk = 0; RFC_chk = 0; RRD_chk = 0;
      RAS_chk0 = 0; RAS_chk1 = 0; RAS_chk2 = 0; RAS_chk3 = 0;
      RCD_chk0 = 0; RCD_chk1 = 0; RCD_chk2 = 0; RCD_chk3 = 0;
      RC_chk0 = 0; RC_chk1 = 0; RC_chk2 = 0; RC_chk3 = 0;
      RP_chk0 = 0; RP_chk1 = 0; RP_chk2 = 0; RP_chk3 = 0;
      $timeformat (-9, 1, " ns", 12);
end

作者: QinQZ 时间: 2021-2-20 17:48
一般是芯片原厂提供的

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